The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device such as a synchronous semiconductor device which operates in synchronism with a clock signal that is supplied from the outside.
Conventionally, as known semiconductor devices which operate in synchronism with a clock signal that is supplied from the outside, there are microprocessor units (MPUs) and synchronous dynamic random access memories (SDRAMs).
FIG. 1 shows a part of an electronic equipment using a MPU and a SDRAM. A MPU 1 and a SDRAM 2 are coupled via a clock signal supply line 3 and a data bus 4. The clock signal supply line 3 supplies a clock signal CLK to the MPU 1 and the SDRAM 2. The data bus 4 forms a transmission line for a data DQ. The MPU 1 has a clock signal input terminal 5 and a data input/output terminal 7. The SDRAM 2 has a clock signal input terminal 6 and a data input/output terminal 8.
FIG. 2 is a timing chart for explaining the operation of the electronic equipment shown in FIG. 1 when the SDRAM 2 outputs data. In FIG. 2, the clock signal CLK has a cycle time t.sub.CLK of 10 ns, and the data DQ is the data that is output from the SDRAM 2.
This SDRAM 2 has a clock signal access time t.sub.CLKA of 6 ns, and an output hold time t.sub.OH of 2 ns. The clock signal access time t.sub.CLKA is a delay time from a rise of the clock signal CLK rises to a time when the data DQ is output. On the other hand, the output hold time t.sub.OH is a time from a rise of the clock signal CLK to a time when holding of the output data DQ ends.
Accordingly, in this case, the cycle time t.sub.CLK of the clock signal CLK is 10 ns and the data transfer speed is 100 MHz, but a set up time t.sub.SU can be set to 4 ns. This set up time t.sub.SU is a time in which the data DQ is settled in advance before the rise of the clock signal CLK.
However, according to the SDRAM 2 described above, the set up time t.sub.SU becomes short if the cycle time t.sub.CLK of the clock signal CLK is made shorter than 10 ns. Further, in some cases, it becomes impossible to secure a sufficiently long set up time t.sub.SU.
For example, FIG. 20 is a timing chart showing a case where the cycle time t.sub.CLK of the clock signal CLK is set to 6 ns and the data transfer speed is 167 MHz. In this case, the set up time t.sub.SU cannot be secured at all. Hence, at the receiving end such as the MPU 1 shown in FIG. 1, for example, it becomes impossible to input the data DQ output from the SDRAM 2.
In this case, it is conceivable to provide a built-in phase locked loop (PLL) circuit so that the same time can be secured as the set up time t.sub.SU for the output data even if the cycle times t.sub.CLK of the clock signals CLK differ when controlling the output timing of the data DQ, as long as the difference in the cycle times t.sub.CLK of the clock signals CLK is within a predetermined range.
However, since the power consumption of the PLL circuit is large, the PLL circuit is unsuited for use for a semiconductor device such as the SDRAM 2 which requires the power consumption to be minimized.